XS40 Tutorial: PC and the XS40 board
This example will show you how to inject signals from the PC into the XS40
boards. The first step is to generate the bit stream for the FPGA:
Now you have to download the bitstream file onto the XS40 board:
- Run Xilinx Foundation Project Manager.
- Click OK to create a new project.
- Type "tut3" for name and browse/select "c:\temp" for
directory and click the HDL flow button followed by OK.
- Download (wrled.vhd,
tut3.ucf) into the "c:\temp\tut3".
- Add the two VHDL files to your project using menu item
"Synthesis - Add HDL Source File(s)...".
- Click the big "Synthesis" button and select "XS40" for Top Level,
"XC4000XL" for Family and "4010XLPC84" for Device, then
- Click the big "Implementation" button, then click Run.
When complete, exit Project Manager. You are done!
Your TA will now explain what this design should do as well as what is
implemented in the VHDL and constraint files. As a reminder, here
is how you inject signals:
- Open a "Command Prompt" terminal and cd to "c:\temp\tut3".
- Make sure your XS40 board is powered up and connected
to the computer.
- Type "xsload tut3.bit" on the prompt and hit "enter".
You are done!
- Type "xsport 00111100" to send 16.
- Type "xsport 00100100" to send 9, etc. (Remember that, in
this example, bits 2, 3, 4, and 5 are used.)