XS40 Tutorial: PC and the XS40 board

This example will show you how to inject signals from the PC into the XS40 boards. The first step is to generate the bit stream for the FPGA:

  1. Run Xilinx Foundation Project Manager.
  2. Click OK to create a new project.
  3. Type "tut3" for name and browse/select "c:\temp" for directory and click the HDL flow button followed by OK.
  4. Download (wrled.vhd, xs40.vhd, tut3.ucf) into the "c:\temp\tut3".
  5. Add the two VHDL files to your project using menu item "Synthesis - Add HDL Source File(s)...".
  6. Click the big "Synthesis" button and select "XS40" for Top Level, "XC4000XL" for Family and "4010XLPC84" for Device, then click Run.
  7. Click the big "Implementation" button, then click Run. When complete, exit Project Manager. You are done!
Now you have to download the bitstream file onto the XS40 board:
  1. Open a "Command Prompt" terminal and cd to "c:\temp\tut3".
  2. Make sure your XS40 board is powered up and connected to the computer.
  3. Type "xsload tut3.bit" on the prompt and hit "enter". You are done!
Your TA will now explain what this design should do as well as what is implemented in the VHDL and constraint files. As a reminder, here is how you inject signals:
  1. Type "xsport 00111100" to send 16.
  2. Type "xsport 00100100" to send 9, etc. (Remember that, in this example, bits 2, 3, 4, and 5 are used.)