Simulation Tutorial: VHDL Design of a 1-bit adder and a 4-bit adder

Aldec Active-HDL Simulation Tutorial:
VHDL Design Of A 1-bit Adder And 4-bit Adder

I. Introduction

In this lab the functionality of a design, in our case a 1-bit adder, is written in a Hardware Description Language (HDL). The correctness of the design is verified at the software level through simulation, thus saving critical design time.

II. Procedure

Creating the 1-bit adder

Start ALDEC Active-HDL

Select "Create New Design" and click OK

Enter adder1 as the name of the project and change the directory to c:\temp and click NEXT

Select "Create Empty Design" and click NEXT

Click FINISH

Double-click on "Add New File" in the Design Browser window

Select "VHDL Source Code" and type in adder1 in the name field, click OK.

The following is the VHDL code for the 1-bit adder. Enter the code as seen below into the empty file. NOTE: All lines that start with "--" are not needed. These are comments to help you better understand what the actual code is doing.

-- Simulation Tutorial
-- 1-bit Adder

-- This is just to make a reference to some common things needed.
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- We declare the 1-bit adder with the inputs and outputs
-- shown inside the port().
-- This will add two bits together(x,y), with a carry in(cin) and 
-- output the sum(sum) and a carry out(cout).
entity BIT_ADDER is
        port( a, b, cin         : in  STD_LOGIC;
              sum, cout         : out STD_LOGIC );
end BIT_ADDER;

-- This describes the functionality of the 1-BIT adder.
architecture BHV of BIT_ADDER is
begin
        
        -- Calculate the sum of the 1-BIT adder.
        sum <=  (not a and not b and cin) or
                        (not a and b and not cin) or
                        (a and not b and not cin) or
                        (a and b and cin);

        -- Calculates the carry out of the 1-BIT adder.
        cout <= (not a and b and cin) or
                        (a and not b and cin) or
                        (a and b and not cin) or
                        (a and b and cin);
end BHV;

Select the File menu and choose Save.

Right click on "add.vhd" in the Design Browser window and select the Compile option.

The code should compile without any problems and the question mark next to the add.vhd file should change into a green check mark. If you get any errors, check the code that you have typed agains the code provided.

Creating testbench for the adder.

The testbench is provided for you and is located here.
Save to c:\temp\adder1\src
Select the Design Menu and choose "Add Files to Design" Add "add_tst.vhd" to the design.
Right click on "add_tst.vhd" in the Design Browser window and select the Compile option.
Left click on the plus next to add_tst.vhd. This will bring us the TEST_ADD entity.
Right click on the TEST_ADD and choose Set as Top-Level

Simulating the design.

Select the "File" menu and choose the "New" option and pick "New Waveform".

In the Desing Browser window select the Structure tab at the bottom of the window.

Click on U1:BIT ADDER and drag all signals to the waveform window.

Select the Simulation menu and choose "Initialize Simulation".

Change the time for simulation form 100 ns to 400 ns by clicking on the up arrow.

Select the Simulation menu and choose Run For

View the simulation to verify that the 1-bit adder functionality is indeed correct.

Creating and testing the 4-bit adder

Create a New Design by selecting the File and choosing New Design

The design should be called adder4 and created in c:\temp. Click on NEXT

Select Create an Empty Design and click on FINISH.

Download the add4.vhd file and the add4_tst.vhd file and save them in the directory c:\temp\adder4\src

Add both of these files to the design

Compile both files and use the testbench (add4_tst.vhd) to simulate the design

View the simulation to verity that the 4-bit adder functionality is correct