Increase in portable electronic devices has created a need for reducing chip power consumption. Chip power can be modeled by the following formula: P = T * C * V * V. Here, V is the supply voltage, T is the average bit transitions per unit time and C is the capacitance of the switching element. The switching elements in a CMOS chip consist of transistors and wires. The capacitance of a wire is 2-3 orders of magnitude greater than that of a transistor. Therefore, reducing the number of transitions on the wires, (even at the expense of increasing transitions on the transistors), reduces total power consumption.
In this lab you will implement a bus encoding scheme called "Bus Invert". The idea here is to encode an N bit string using N+1 bits. Using the 2^(N-1) redundant words, we can pick representations for the values 0, 1, 2, ... 2^N-1 that minimize the average distance between all pairs of words. Your TA will describe the details of "Bus Invert".
You will need to build two black boxes that will encode/decode 8 bit words. Your encoder will have an 8 bit input and a 9 bit output. Conversely, your decoder will have a 9 bit input and a 8 bit output. Both entities will have reset, clock, start and done signals as used in the previous labs. In your testbench, you will, instanciate an encoder and a decoder. Then, you will chain the output of your encoder to the input of your decoder. Likewise, you will feed the done signal of your encoder to the start signal of your decoder. Note that to minimally test your designs you must encode/decode at least 2 8-bit words. Do you know why?
Your are required to write synthesizable VHDL and use Synopsys synthesis tools to generate and simulate gate level designs.
Convince your TA that your designs are correct and perhaps even plausible.