2-Bit Counter

I. Introduction

For this lab, you are required to write a vhdl description of a finite state machine (FSM) and a testbench to show its correctness.

Inputs into your machine will be the following:

II. Procedure

implementation and simulation

  1. Come up with the FSM that will describe how this design should function.
  2. Translate the FSM into a VHDL description
  3. Test your design by writing a VHDL testbench and observing the results in ALDEC Active-VHDL.
  1. Once you have verified the results using Aldec VHDL, check out an XS40 board to download your code.
  2. The clock on the XS40 is too fast to verify your counter. You will need to add a clock divider ( clkdiv.vhd) to your code. This will slow down the clock from your XS40 board to your counter so that you can observe the results. The output from the clock divider will only pulse once every second. The schematic below will give you an idea of how to connect the clock divider.
  3. Create a .ucf file for your design.
  4. Generate a bit file using Xilinx and download it unto your XS40 board.
  5. Verify your results.