-- -- Tony Givargis -- --**************************************************************************-- library IEEE; use IEEE.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.all; --**************************************************************************-- entity WRLED is port(val : in UNSIGNED (3 downto 0); led : out STD_LOGIC_VECTOR (6 downto 0)); end WRLED; --**************************************************************************-- architecture WRLED_ARCH of WRLED is begin process(val) begin case val is when "0000" => led <= "1110111"; when "0001" => led <= "0100100"; when "0010" => led <= "1011101"; when "0011" => led <= "1101101"; when "0100" => led <= "0101110"; when "0101" => led <= "1101011"; when "0110" => led <= "1111011"; when "0111" => led <= "0100101"; when "1000" => led <= "1111111"; when "1001" => led <= "1101111"; when "1010" => led <= "0111111"; when "1011" => led <= "1111010"; when "1100" => led <= "1010011"; when "1101" => led <= "1111100"; when "1110" => led <= "1011011"; when "1111" => led <= "0011011"; when others => led <= "0001000"; end case; end process; end WRLED_ARCH;