-- lights.vhd -- 2-bit counter entity -- ********************************************************************** -- library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.all; entity counter is -- declare input and outputs ports for the counter end counter; architecture count_beh of counter is -- add behavioral description of counter end count_beh; -- ********************************************************************** -- -- 2-4 decoder entity -- ********************************************************************** -- library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.all; entity decoder is -- declare input and outputs ports for the decoder end decoder; architecture dec_beh of decoder is -- add behavioral description of decoder end dec_beh; -- ********************************************************************** -- -- top level entity -- ********************************************************************** -- library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.all; entity XS40 is port( clk : in STD_LOGIC; rst : in STD_LOGIC; output: out UNSIGNED(3 downto 0) ); end XS40; architecture XS40_ARCH of XS40 is -- insert components declarations here -- insert signal declarations here begin -- instantiate and map components here end XS40_ARCH; -- ********************************************************************** --