• VHDL Books

There are dozens of great books talking about VHDL modeling, simulation and synthesis. Here are some of them:
 

(1) VHDL Made Easy by Pellerin & Taylor (2) Digital Design System Design with VHDL by Mark Zwolinski (3) Introductory VHDL from Simulation to Synthesis by Yalamanchili (4) VHDL Coding and Logic Synthesis with Synopsys by Weng Fook Lee (5) Digital Design and Modeling with VHDL and Synthesis by K. C. Chang (6) VHDL Coding Styles and Methodologies by Ben Cohen (7) VHDL Design Representation and Synthesis by James Armstrong (8) Digital Systems Design with VHDL and Synthesis by K.C. Chang

A nice introduction


 

• VHDL Tutorials

(1) A Tutorial by Dr. Wolfram H. Glauert from German 
(2) An Introductory VHDL Tutorial by Green Mountain Computing Systems
(3) A small VHDL Tutorial by Dr. Ian McCrum from UK 
(4) Another VHDL Guide, which includes nice block diagrams. 
(5) A Hardware Engineer’s Guide to VHDL by Doulos 
(6) VHDL Synthesis Tutorial by Bob Reese from MSU
(7) VHDL MINI-REFERENCE by NCSU
(8) A classical introduction into VHDL and hardware design by Peter J. Ashenden
 
 
• VHDL Examples

(1) VHDL examples for synthesis by Dr. Chang from Korea
(2) VHDL - Examples and Microprocessor Models from UK 
(3) Lots of examples (pdf doc) both on VHDL and Verilog from Actel
(4) Essential VHDL Design Examples
(5) Advanced Electronic Design Automation: Examples of VHDL Descriptions by AMI
(6) Example of Adder and Multiplexor with explaination
(7) VHDL materials by Dr Amit Bergman at UCSD
 
 
• CAD/EDA Tools Guides

(1) Synopsys Synthesis Tutorial from NCSU (pdf doc)
(2) Synopsys Tools from SCU
(3) Digital Logic Synthesis Using Synopsys and Xilinx from Canada
(4) Synopsys Synthesis Tools from Hawaii U
(5) Mentor Graphics Tutorials
(6) BYU Mentor Tutorials Home Page
(7) Xilinx FPGA Synthesis at Duke
 
 
• Software Download

(1) Xilinx Foundation/Alliance Series and Xilinx Student Edition book 
(2) Actel DeskTOP free download 
(3) Synopys FPGA Express Evaluation Download
(4) Aldec Active-HDL Evaluation 4.2
(5) Synplify FPGA synthesis solution 
(6) Alliance VLSI CAD System
(7) Protel 99 SE Trial Version (board level design) 
 
 
• Others

(1) VHDL, Verilog and C Language Compared & Contrasted
(2)  convert VHDL/Verilog into HTML with color highlighting of keywords etc. 

Created by Weijun Zhang (weijun_92507@yahoo.com), at UC, Riverside, 03/2001