library IEEE,lsi_10k; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_textio.all; use lsi_10k.COMPONENTS.all; package CONV_PACK_D_latch is -- define attributes attribute ENUM_ENCODING : STRING; end CONV_PACK_D_latch; library IEEE,lsi_10k; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_textio.all; use lsi_10k.COMPONENTS.all; use work.CONV_PACK_D_latch.all; entity D_latch is port( data_in, enable : in std_logic; data_out : out std_logic); end D_latch; architecture SYN of D_latch is component LD1P port( D, G : in std_logic; Q, QN : out std_logic); end component; signal n8 : std_logic; begin data_out_reg : LD1P port map( D => data_in, G => enable, Q => data_out, QN => n8); end SYN;