A Simplified VHDL UART

Introduction

In embedded systems, the processor that we choose for our design may not come with built-in peripherals. Therefore, designers will have to implement these devices in hardware keeping in mind that they will need to interface to the processor. In this lab we will design a simplified UART (Universal Asynchronous Reciever Transmitter) in VHDL and download it to the FPGA on the XS40 baord.

Serial communication is often used either to control or to receive data from an embedded microprocessor. Serial communication is a form of I/O in which the bits of a byte begin transferred appear one after the other in a timed sequence on a single wire. Serial communication has become the standard for intercomputer communication. In this lab, we'll try to build a serial link between 8051 and PC using RS232.

RS232C:

The example serial waveforms in Fig 1 show the waveform on a single conductor to transmit a byte (0x41) serially. The upper waveform is the TTL-level waveform seen at the transmit pin of 8051. The lower waveform shows the same waveform converted to RS232C levels. The voltage level of the RS232C are used to assure error-free transmission over greater distances than would be possible with TTL levels.
As shown in Fig 1, each byte is preceded by a start bit and followed by one stop bit. The start and stop bits are used to synchronize the serial recievers. The data byte is always transmitted least-significant-bit first. For error checking it is possible to include a parity bit as well, just prior to the stop bit. The bits are transmitted at specific time intervals determined by the baud rate of the serial signal. The baud rate is the reciprocal of the time to send 1 bit. Error-free serial communication requires that the baud rate, number of data bits, number of stop bits, and presence or absence of a parity bit be the same at the transmitter and at the receiver.


Fig 1. Serial Waveforms

RS232 connector:

PCs have 9pin/25pin male SUB-D connectors. The pin layout is as follows (seen from outside your PC): 


        1                         13         1         5
      _______________________________      _______________
      \  . . . . . . . . . . . . .  /      \  . . . . .  /
       \  . . . . . . . . . . . .  /        \  . . . .  /
        ---------------------------          -----------
        14                       25           6       9

 Name (V24)  25pin  9pin  Dir  Full name               Remarks
--------------------------------------------------------------------------
    TxD         2     3    o   Transmit Data
    RxD         3     2    i   Receive Data
    RTS         4     7    o   Request To Send
    CTS         5     8    i   Clear To Send
    DTR        20     4    o   Data Terminal Ready
    DSR         6     6    i   Data Set Ready
    RI         22     9    i   Ring Indicator
    DCD         8     1    i   Data Carrier Detect
    GND         7     5    -   Signal ground
     -          1     -    -   Protective ground       Don't use this one
                                                       for signal ground!
The most important lines are RxD, TxD, and GND. Others are used with modems, printers and plotters to indicate internal states.
In this lab, we are going to use serial.exe, to communicate between the PC and the 8051.

UART Clock Divider:

The UART that we are designing will be transmitting data at a rate of 1200 baud, or 1200 bps. However, since the FPGA and 8051 on the XS40 board operates at 12 MHz, simply transmitting one bit every clock cycles will be too fast. Therefore, we will need to create a clock divider that will be used by the UART to transmit one bit per cycle. The input to the clock divider will be a 12 MHz clock and the output should be a 1200 Hz clock.

Apparatus Required:

  1. 0.1 mF capacitors(6)
  2. LT1130CN
  3. Serial Connector
  4. Serial Cable
  5. XS40 Board

Schematic:

Procedure:

  1. Download the following files:
  2. Modify main.c to send each character and wait for the acknowledge signal from the UART.
  3. Modify uartclkdiv.vhd to complete the functionality of the clock divder to create a clock for 1200 bps (1200 Hz).
  4. Modify uart.vhd to complete the UART.
    NOTE: Becuase the CPU read/write process and UART transmit process have different clock signals as input, it will be neccessary to use handshaking signals between the two.
  5. Compile, synthesisze, and download the 8051 program and UART to the FPGA.
    NOTE:If you are unsure of how to compile and download, refer to the Music Generator Lab