Watchdog Timer


In this lab you will design a hardware watch dog timer. A distinguishing characteristic of embedded systems is that they will automatically start "executing" on power up. Such systems are designed to start executing a single software application (firmware) whenever power is applied to the unit. As we all know, software systems can be buggy and often enter unwanted infinite loops, therefore freezing the system. A watch dog timer is used to reset (automatically) an embedded system when it freezes.

A watch dog timer (WDT) is a count down timer. The simplest WDT will have a programmable register (say memory mapped) that contains the count down start value. The WDT will start counting down from this start value until it reaches some lower point (say zero). At this point, it generate a pulse to reset the attached micro-processor. A write operation to the count down start value will reset the timer, i.e., the timer will start counting down all over again from the start value. For this lab you are to design a WDT to be implemented on FPGA. Here are the specs for your WDT.

  1. Count down happens once every one second.
  2. One memory mapped register will allow for programming the start value.
  3. The default value for the initial value register is 255.
You are to write a buggy program in order to test your WDT. Your 8031 program should perform some computation, e.g., write 1, 2, 3 ... to the LED and at some point enter an infinite loop. During normal operation, the 8031 program must periodically (up to 254 second long cycles) write to the WDT's initial value register to avoid unnecessary resets.

Demo Output

You should be able to demonstrate to your TA how your embedded system is reset after it has enters an infinite loop.