Xlinix Synthesis Tutorial:
Using the 7-segment display
This tutorial shows how to synthesize and download a design unto
an XS40 board. The purpose of this lab is to get the 7-seg LED
connected to the FPGA to count from 0 to F.
Generating the bit stream for the FPGA:
- Run Xilinx Foundation Project Manager.
- Click OK to create a new project.
- Type "tut1" for name and browse/select "c:\temp" for
directory and click the HDL flow button followed by OK
- Download (wrled.vhd,
- Add the two VHDL files to your project using menus item
"Synthesis - Add HDL Source Files(s)...".
- Click the big "Synthesis" button and select "XS40" for Top
Level, "XC4000XL" for Family and "4010XLPC84" for Device, then
- Click the big "Implementation" button, then click Run. When
complete, exit Project Manager.
You are done!
Downloading bitstream file unto the XS40 board:
- Open a "Command Prompt" terminal and cd to "c:\temp\tut1".
- Make sure your XS40 board is powered up and connected to the
- Type "xsload tut1.bit" on the prompt and hit "enter".
- Pull out jumper J4, the LED should
be counting from 0 to F.