Xlinix Synthesis Tutorial:
Using the 7-segment display

This tutorial shows how to synthesize and download a design unto an XS40 board. The purpose of this lab is to get the 7-seg LED connected to the FPGA to count from 0 to F.

Generating the bit stream for the FPGA:

  1. Run Xilinx Foundation Project Manager.
  2. Click OK to create a new project.
  3. Type "tut1" for name and browse/select "c:\temp" for directory and click the HDL flow button followed by OK
  4. Download (wrled.vhd, clkdiv.vhdtut1.ucf) into "c:\temp\tut1".
  5. Add the two VHDL files to your project using menus item "Synthesis - Add HDL Source Files(s)...".
  6. Click the big "Synthesis" button and select "XS40" for Top Level, "XC4000XL" for Family and "4010XLPC84" for Device, then click Run.
  7. Click the big "Implementation" button, then click Run. When complete, exit Project Manager.
    You are done!

Downloading bitstream file unto the XS40 board:

  1. Open a "Command Prompt" terminal and cd to "c:\temp\tut1".
  2. Make sure your XS40 board is powered up and connected to the computer.
  3. Type "xsload tut1.bit" on the prompt and hit "enter".
  4. Pull out jumper J4, the LED should be counting from 0 to F.