Lab Index

Lab Index

Provided below are a series of labs which can be used in conjuction with the Embedded Systems Design book. The procedures, schematics, materials, and steps have been provided as resources for an instructor or teaching assistant utilizing this book.

Helpful Links

Lab Setup

Master Components List

Additional Files/Handouts Needed for Labs

Lab Assignments

Chapter 1 - Introduction

Lab Title Lab Description

No labs

Chapter 2 - Custom single-purpose processors: Hardware

Lab Title Lab Description

Tutorial:
Aldec Active-HDL Simulation Code is provided for a 1-bit adder and a corresponding testbench. Steps are given to show students how to simulate the design. Code is provided for a 4-bit added built using the 1-bit adder previously used. A corresponding testbench is also included. Students simulate the 4-bit adder design and check to see if the functionality is correct.

XS40 Tutorial:
VHDL Synthesis Tutorial shows students how to synthesize and download VHDL code unto an XS40 board. Tutorial provides code for a counter the counts up form 0 to F. The tutorial gives steps showing how to synthesize the code provided using Xilinx FPGA express to generate a bit stream. Then the bit stream is downloaded unto the XS40 board and the 7-segment LED on the board will count repeatedly from 0 to F.

XS40 Tutorial:
Onboard micro-controller (8031) Tutorial shows students how to control the onboard micro-controller (8031) connected to the FPGA.

XS40 Tutorial:
Sending signals from the PC Tutorial shows students how to inject signals from the PC into the XS40 boards.

Introduction to FPGA's with schematic capture The purpose of this lab is to design a 7-segment decoder using AND, OR, NAND, NOR, XOR, and XNOR gates. The circuit will read in a 4-bit binary value and output 7 signals (a through g), which correspond to a segment on the 7 segment display. The decoder will accept the binary value and light the appropriate led's so that the equivalent decimal value appears.

Introduction to FPGA's using VHDL Follow-up to the "Introduction to FPGA's with schematic capture" lab. The 7-segment decoder circuit draw in the previous lab is translated into VHDL. The VHDL decoder is written structurally and simulated to test for correctness.
Introduction to VHDL Simulation and Synthesis:
Blinking LEDs Lab Lab in which the student will implement a behavioral description of a 2-bit counter whose output is fed to a 2-to-4 decoder. The decoder is then wired to 4 led's. As it counts the led's light up according to the binary equivalent. The design is first simulated in ALDEC Acitve-HDL to check the functionality. Then the design is synthesized using Xilinx FPGA express and downloaded unto an XS40 board.

7-Segment Decoder: Behavioral Description Follow-up to the "Introduction to FPGA's using VHDL" lab. In this lab the 7-segment decoder is re-written so that it is a behavioral description. The behavioral VHDL decoder is simulated to test for correctness. The design is then downloaded unto an XS40 board and tested once again.

ALU Design The purpose of this lab is to build a 2-bit ALU. The ALU is written behaviorally. It should take in two numbers and be able to add the numbers, subtract the numbers, NOR the numbers, or NAND the numbers. A test bench is written for the design so that it can be simulated in ALDEC Acitve-HDL and tested for correctness.

2-bit counter The purpose of this lab is to write a VHDL description of 2-bit counter as a finite state machine (FSM). The 2-bit counter has several inputs such as clk, rst, enable, load, ... and should be able to reset, accept an input, count-up or count-down, etc... A testbench is written and the design is simulated using ALDEC to test for correctness.

FSM + D: GCD calculator The purpose of this lab is to write a VHDL description of a GCD (greatest common divisor) calculator. The calculator accepts two numbers from the user/testbench and outputs the GCD. The calculator is divided into two parts - a controller and a datapath. The controller is the FSM which issues commands based on the current state and the external inputs. This portion can be a behavioral description. The datapath contains the netlist of functional units like mulitplexors, registers, subtractors, and a comparator. The algorithim to implement the GCD calculator is provided. A testbench is written and the design is simulated using ALDEC to test for correctness.

FSM + D: Parallel to Serial Convertor The purpose of this lab is to write a VHDL description of a parallel to serial convertor as an FSMD. The parallel to serial convertor will accept an eight-bit number and send one bit of data over the data line per clock cycle. There is also a go bit which tells the convertor to start transmitting data. A testbench is written and the design is simulated using ALDEC to test for correctness.

FSM to FSM+D: Soda Machine Controller The purpose of this lab is to implement a soda machine controller. The cost of a soda is 75 cents. The machine accepts quarters, dimes, and nickles. As the user feeds in the coins, the controller keeps tract of how much was inserted. Once the 75 cents have been inserted, the controller releases a soda. To simplify the lab, change will not be given. In addition there should be a reset and an enable to the system. A testbench is written and the design is simulated using ALDEC to test for correctness.

VHDL calculator The purpose of this lab is to implement a finite state machine in VHDL to perform simple calculations like addition, subtraction, and multiplication. A testbench is written to check the functionality of the design. The program is downloaded unto the XS40 board and DIP switches are used to vary the inputs.

Watchdog Timer Designing a hardware watchdog timer.

Also see Web Resources for the VHDL Tutorial: Learn By Example.

Chapter 3 - General-purpose processors: Software

Lab Title Lab Description

Microprocessor The purpose of this lab is to implement a microprocessor in VHDL. The microprocessor, unlike a single purpose processor, can accomplish various tasks via programs written in an Instruction Set that the microprocessor can recognize. Most processors are built from a controller, datapath, and memory. For the purposes of this lab we will deviate from this processor architecture and have the memory integrated into the controller. An simplified instruction set is provided for this lab. Some skeletal VHDL code is provided for the controller, datapath, and, CPU as a starting point for students. A one's count algorithim is implemented. This algorithim counts the number of 1's appearing in an n-bit binary number. A testbench is written and the design is simulated using ALDEC to test for correctness.

8051 tutorial Tutorial provides code to blink an led using the 8051. The tutorial shows students how to compile the program using the c51 compiler, then run the program using the PDS51 emulation software.

8051 stand alone chip tutorial Tutorial provides code to blink an led using the 8051 stand alone chip. The tutorial shows students how to compile the program using the c51 compiler, burn a copy of the program onto an 8051 chip, and the connections needed to run the stand alone chip.

Music Generator The purpose of this lab is to design a peripheral device that plays musical notes.

Day of the Week The purpose of this lab is to design a FSM when given day, month, and year will output the day of the week.

Prefix Length Describe, at FSMD level, an entity that will compute the length of the prefix of two 16 bit binary strings.

Virtual Clock Implement a software Real-Time Clock, i.e., a Virtual Clock (VC). One possible implementation of a VC is to tie into a timer interrupt and accordingly update time variables such as hour, minute, etc.

Instruction Set Simulator Use a simple instruction-set simulator.

Chapter 4 - Standard single-purpose processors: Peripherals

Lab Title Lab Description

Implementing a 4bit Counter using an 8051 and Interfacing it to an LCD In this lab, students will learn how to write a simple C program for 80X51 micro-controller, compile it using the C51 compiler, emulate it on an emulator using PDS51, and learn how to use an LCD (Liquid Crystal Display). The program will be used to control a simple 4-bit up-down counter, capable of counting from 0 to 15. At each step the count should be displayed in decimal format on the LCD.

Implementing a Calculator Using Peripherals Like a Keypad and an LCD In this lab, the student will build a simple calculator using the keypad as an input and the LCD as an output peripheral. After debugging and testing your program, the student will have to burn the compiled program to a standalone 8051 chip at the end of the lab.

A/D Conversion The purpose of this lab is to be able to implement analog to digital conversion using the ADC0804LCN 8-bit A/D converter. The student will design a circuit and program the chip so that when an analog signal is given as input, the equivalent digital voltage is displayed on an LCD display. Thus, in effect, the circuit should function like a simple voltmeter.

Stepper Motor The purpose of this lab is to control a stepper motor, with instructions received from the PC via a serial communication link to the 8051.

4-Bit Counter with Seven Segment Display Implement a 4-bit counter using an 8051 and a seven segment display

Decimal Counter and Multiplexing the Output Implement a decimal counter which counts from 0 to 99 using two 7-segment display and an 8051.

Decimal Counter and Time Multiplexing Implement a decimal counter which counts from 0 to 99 using two 7-segment display and an 8051. In this lab only one port is used so we must multiplex the output.

Keypad Scan Read input from a keypad and display the corresponding key pressed unto a 7-segment dispaly.

Reflex Timer Build a Reflex Timer by using the timers and interrupts avaiable on the 8051. Reflex Timer will measure a person reaction time to stimulus in milliseconds.

Chapter 5 - Memory

Lab Title Lab Description

Memory Mapped I/O Interfacing the 8031 to the FPGA by using memory-mapped IO

Memory Lab Using EEPROMs

8051 external memory Using the 8051 and some sort of external memory. Read and write to the external memory ????

Chapter 6 - Interfacing

Lab Title Lab Description

Interfacing: Converting 8-bit LCD communication to 4-bit Convert the interface to an LCD from a 8-bit interface to a 4-bit interface.

Serial Communication The purpose of this lab is to establish serial communication between the PC and the 8051.

A Simplified VHDL UART In this labs the students design a VHDL UART to send data to the PC.

Temperature Sensor Acquisition Module The purpose of the lab is to build a device which samples the temperature every second, storing the value on the EEPROM. The students will also have to implement I2C protocol to communicate with the temperature download program located on the PC.

ISA Bus Lab VHDL implementation ISA bus protocol

I²C Bus Lab VHDL implementation I²C bus protocol

Bus Invert In this lab you will implement a bus encoding scheme called "Bus Invert". The idea here is to encode an N bit string using N+1 bits. Using the 2^(N-1) redundant words, we can pick representations for the values 0, 1, 2, ... 2^N-1 that minimize the average distance between all pairs of words.

Chapter 7 - Digital Camera Example

Lab Title Lab Description

See Web Resources for the digital camera source files.

Chapter 8 - State machine and concurrent process models

Lab Title Lab Description

Coming later

Chapter 9 - Control systems

Lab Title Lab Description

Coming later

Chapter 10 - IC technology

Lab Title Lab Description

No labs

Chapter 11 - IC tehcnology

Lab Title Lab Description

No labs

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TABLE OF CONTENTS

LABS

SLIDES

Lab Title	Lab Description
Tutorial: Aldec Active-HDL Simulation	Code is provided for a 1-bit adder and a corresponding testbench. Steps are given to show students how to simulate the design. Code is provided for a 4-bit added built using the 1-bit adder previously used. A corresponding testbench is also included. Students simulate the 4-bit adder design and check to see if the functionality is correct.
XS40 Tutorial: VHDL Synthesis	Tutorial shows students how to synthesize and download VHDL code unto an XS40 board. Tutorial provides code for a counter the counts up form 0 to F. The tutorial gives steps showing how to synthesize the code provided using Xilinx FPGA express to generate a bit stream. Then the bit stream is downloaded unto the XS40 board and the 7-segment LED on the board will count repeatedly from 0 to F.
XS40 Tutorial: Onboard micro-controller (8031)	Tutorial shows students how to control the onboard micro-controller (8031) connected to the FPGA.
XS40 Tutorial: Sending signals from the PC	Tutorial shows students how to inject signals from the PC into the XS40 boards.
Introduction to FPGA's with schematic capture	The purpose of this lab is to design a 7-segment decoder using AND, OR, NAND, NOR, XOR, and XNOR gates. The circuit will read in a 4-bit binary value and output 7 signals (a through g), which correspond to a segment on the 7 segment display. The decoder will accept the binary value and light the appropriate led's so that the equivalent decimal value appears.
Introduction to FPGA's using VHDL	Follow-up to the "Introduction to FPGA's with schematic capture" lab. The 7-segment decoder circuit draw in the previous lab is translated into VHDL. The VHDL decoder is written structurally and simulated to test for correctness.
Introduction to VHDL Simulation and Synthesis: Blinking LEDs Lab	Lab in which the student will implement a behavioral description of a 2-bit counter whose output is fed to a 2-to-4 decoder. The decoder is then wired to 4 led's. As it counts the led's light up according to the binary equivalent. The design is first simulated in ALDEC Acitve-HDL to check the functionality. Then the design is synthesized using Xilinx FPGA express and downloaded unto an XS40 board.
7-Segment Decoder: Behavioral Description	Follow-up to the "Introduction to FPGA's using VHDL" lab. In this lab the 7-segment decoder is re-written so that it is a behavioral description. The behavioral VHDL decoder is simulated to test for correctness. The design is then downloaded unto an XS40 board and tested once again.
ALU Design	The purpose of this lab is to build a 2-bit ALU. The ALU is written behaviorally. It should take in two numbers and be able to add the numbers, subtract the numbers, NOR the numbers, or NAND the numbers. A test bench is written for the design so that it can be simulated in ALDEC Acitve-HDL and tested for correctness.
2-bit counter	The purpose of this lab is to write a VHDL description of 2-bit counter as a finite state machine (FSM). The 2-bit counter has several inputs such as clk, rst, enable, load, ... and should be able to reset, accept an input, count-up or count-down, etc... A testbench is written and the design is simulated using ALDEC to test for correctness.
FSM + D: GCD calculator	The purpose of this lab is to write a VHDL description of a GCD (greatest common divisor) calculator. The calculator accepts two numbers from the user/testbench and outputs the GCD. The calculator is divided into two parts - a controller and a datapath. The controller is the FSM which issues commands based on the current state and the external inputs. This portion can be a behavioral description. The datapath contains the netlist of functional units like mulitplexors, registers, subtractors, and a comparator. The algorithim to implement the GCD calculator is provided. A testbench is written and the design is simulated using ALDEC to test for correctness.
FSM + D: Parallel to Serial Convertor	The purpose of this lab is to write a VHDL description of a parallel to serial convertor as an FSMD. The parallel to serial convertor will accept an eight-bit number and send one bit of data over the data line per clock cycle. There is also a go bit which tells the convertor to start transmitting data. A testbench is written and the design is simulated using ALDEC to test for correctness.
FSM to FSM+D: Soda Machine Controller	The purpose of this lab is to implement a soda machine controller. The cost of a soda is 75 cents. The machine accepts quarters, dimes, and nickles. As the user feeds in the coins, the controller keeps tract of how much was inserted. Once the 75 cents have been inserted, the controller releases a soda. To simplify the lab, change will not be given. In addition there should be a reset and an enable to the system. A testbench is written and the design is simulated using ALDEC to test for correctness.
VHDL calculator	The purpose of this lab is to implement a finite state machine in VHDL to perform simple calculations like addition, subtraction, and multiplication. A testbench is written to check the functionality of the design. The program is downloaded unto the XS40 board and DIP switches are used to vary the inputs.
Watchdog Timer	Designing a hardware watchdog timer.
Also see Web Resources for the VHDL Tutorial: Learn By Example.

Lab Title	Lab Description
Microprocessor	The purpose of this lab is to implement a microprocessor in VHDL. The microprocessor, unlike a single purpose processor, can accomplish various tasks via programs written in an Instruction Set that the microprocessor can recognize. Most processors are built from a controller, datapath, and memory. For the purposes of this lab we will deviate from this processor architecture and have the memory integrated into the controller. An simplified instruction set is provided for this lab. Some skeletal VHDL code is provided for the controller, datapath, and, CPU as a starting point for students. A one's count algorithim is implemented. This algorithim counts the number of 1's appearing in an n-bit binary number. A testbench is written and the design is simulated using ALDEC to test for correctness.
8051 tutorial	Tutorial provides code to blink an led using the 8051. The tutorial shows students how to compile the program using the c51 compiler, then run the program using the PDS51 emulation software.
8051 stand alone chip tutorial	Tutorial provides code to blink an led using the 8051 stand alone chip. The tutorial shows students how to compile the program using the c51 compiler, burn a copy of the program onto an 8051 chip, and the connections needed to run the stand alone chip.
Music Generator	The purpose of this lab is to design a peripheral device that plays musical notes.
Day of the Week	The purpose of this lab is to design a FSM when given day, month, and year will output the day of the week.
Prefix Length	Describe, at FSMD level, an entity that will compute the length of the prefix of two 16 bit binary strings.
Virtual Clock	Implement a software Real-Time Clock, i.e., a Virtual Clock (VC). One possible implementation of a VC is to tie into a timer interrupt and accordingly update time variables such as hour, minute, etc.
Instruction Set Simulator	Use a simple instruction-set simulator.

Lab Title	Lab Description
Implementing a 4bit Counter using an 8051 and Interfacing it to an LCD	In this lab, students will learn how to write a simple C program for 80X51 micro-controller, compile it using the C51 compiler, emulate it on an emulator using PDS51, and learn how to use an LCD (Liquid Crystal Display). The program will be used to control a simple 4-bit up-down counter, capable of counting from 0 to 15. At each step the count should be displayed in decimal format on the LCD.
Implementing a Calculator Using Peripherals Like a Keypad and an LCD	In this lab, the student will build a simple calculator using the keypad as an input and the LCD as an output peripheral. After debugging and testing your program, the student will have to burn the compiled program to a standalone 8051 chip at the end of the lab.
A/D Conversion	The purpose of this lab is to be able to implement analog to digital conversion using the ADC0804LCN 8-bit A/D converter. The student will design a circuit and program the chip so that when an analog signal is given as input, the equivalent digital voltage is displayed on an LCD display. Thus, in effect, the circuit should function like a simple voltmeter.
Stepper Motor	The purpose of this lab is to control a stepper motor, with instructions received from the PC via a serial communication link to the 8051.
4-Bit Counter with Seven Segment Display	Implement a 4-bit counter using an 8051 and a seven segment display
Decimal Counter and Multiplexing the Output	Implement a decimal counter which counts from 0 to 99 using two 7-segment display and an 8051.
Decimal Counter and Time Multiplexing	Implement a decimal counter which counts from 0 to 99 using two 7-segment display and an 8051. In this lab only one port is used so we must multiplex the output.
Keypad Scan	Read input from a keypad and display the corresponding key pressed unto a 7-segment dispaly.
Reflex Timer	Build a Reflex Timer by using the timers and interrupts avaiable on the 8051. Reflex Timer will measure a person reaction time to stimulus in milliseconds.

Lab Title	Lab Description
Memory Mapped I/O	Interfacing the 8031 to the FPGA by using memory-mapped IO
Memory Lab	Using EEPROMs
8051 external memory	Using the 8051 and some sort of external memory. Read and write to the external memory ????

Lab Title	Lab Description
Interfacing: Converting 8-bit LCD communication to 4-bit	Convert the interface to an LCD from a 8-bit interface to a 4-bit interface.
Serial Communication	The purpose of this lab is to establish serial communication between the PC and the 8051.
A Simplified VHDL UART	In this labs the students design a VHDL UART to send data to the PC.
Temperature Sensor Acquisition Module	The purpose of the lab is to build a device which samples the temperature every second, storing the value on the EEPROM. The students will also have to implement I2C protocol to communicate with the temperature download program located on the PC.
ISA Bus Lab	VHDL implementation ISA bus protocol
I²C Bus Lab	VHDL implementation I²C bus protocol
Bus Invert	In this lab you will implement a bus encoding scheme called "Bus Invert". The idea here is to encode an N bit string using N+1 bits. Using the 2^(N-1) redundant words, we can pick representations for the values 0, 1, 2, ... 2^N-1 that minimize the average distance between all pairs of words.

Lab Title	Lab Description
See Web Resources for the digital camera source files.